1. Field of the Invention
This invention relates to a floating point processor and more particularly to a sticky signal generator for generating a sticky signal in order to improve the reliability of operation of different-sized operands.
2. Description of the Related Art
Referring to the standard of Institute of Electrical and Electronics Engineers ("IEEE standard") on floating point processing, five exceptional processing events on floating point processing are defined in it. The five exceptional events include "Underflow" of operand data, "Overflow" of operand data, "Division by zero", "Data Inexactness" due to the data rounding and "Invalid Operation" which means that the operation is not defined.
According to the above mentioned IEEE tandard, in case one or more of the above five events happens during a certain operation being processed, just the fact that one or more of the exceptional events has happened is recorded in a predetermined flag and the operation keeps being processed.
Every system which includes floating point unit ("FPU") is recommended to follow IEEE standard No. 754 ("IEEE 754"), which is related to the floating point operation. For example, when an FPU is used in a microprocessor, a digital signal processor ("DSP"), or a microcontroller, etc., the IEEE 754 should be followed in order for the data compatibility.
Generally, in order to process floating point operands in an FPU, above all things, the numbers of bits of the operands are to be matched. In case the numbers of bits of the inputted operands are different, the two operands are called "different-sized". When two different-sized operands are used for a certain operation, the number of bits of one operand ("bigger operand") which has more number of bits than that of another operand ("smaller operand") is reduced to the number of bits of the smaller operand.
Conventionally, shift registers can be used to reduce the number of bits of the bigger operand. However, while reducing the number of bits of an operand by shift registers, several bits out of the shifted bits are discarded and if one or more of logic "1" bits are included the discarded bits, the result of the operation will be incorrect.
Therefore, in order to maintain the correctness of the operation of the different-sized operands, the information on the discarded logic "1" bits is set into a flag bit and the information is used to compensate the result of the operation during or after the process of the operation. A signal used to represent the information on the discarded logic "1" bits is called a "sticky signal".
Conventionally, if the number (e.g. integer "N") of bits of an operand is a multiple of 2 (two), a shift register of which the size is "2N" is needed to store the discarded bits. Otherwise, the number (e.g. integer "M") of bits of an operand is not a multiple of 2, a shift register of which the size is "M"+"K" is needed, where "K" is a multiple of 2 larger than "M". In other words, when an input operand data is not a multiple of 2, much larger size of shift register is needed.
For example, if the size of an input operand data is 64 bits which is a multiple of 2, the actual size of the operand becomes 68 bits including a Guard bit, a Round bit, a Sticky bit and an overflow bit which are specified in IEEE 754 for internal processing. So, a shift register of which the size is 128 bits is needed, so that the needed size of the shift register becomes 196 bits in total.
Therefore, the size of the shift register used in operation of two different-sized operands will be larger than the size of the operands, so that the shifting process will be slow. And, the slow shifting process results in decreasing the system performance. Further, the large size of the shift register makes the layout of the chip large and complex.